EDN

MMCM and PLL Dynamic Reconfiguration

This application note describes the information necessary to reconfigure the MMCM or PLL and provides a reference design that implements all of the algorithms covered. The PLL and MMCM share very ...
Design-Reuse

Improve FPGA communications interface clock jitters with external PLLs

Over a few short years, FPGA technology has advanced significantly. These devices have become extremely complex. FPGA blocks continue to maintain the phase-locked loop (PLL) technology capable of ...
EDN

Xilinx Virtex-6 FPGA User Guide Lite

Editor's Note As with similar “lite” user guides published by Programmable Logic DesignLine previously, this guide is intended to bridge the gap between a datasheet and a full, 1,000+ page user guide.
Electronic Design

Select The Right PLL-based Oscillator For Your Timing Application

More than 10 years ago, the frequency control industry introduced PLL-based (phase-locked loop) oscillators, an innovation that pioneered several features previously unavailable with traditional ...